How to use vivado ila

This tutorial covers utilizing the Built-in Logic Analyzer (ILA) and Digital Enter/Output (VIO) cores to debug and monitor your VHDL design within the Xilinx Vivado IDE.In lots of circumstances, designers are in want to carry out on-chip verification. That’s, gaining entry to an inner sign’s habits of their FPGA design for verification functions.Reading: How to use vivado ilaOne choice is to convey these indicators to the FPGA pins and join them to LEDs to see their habits visually. This feature is straightforward, quick, and works nicely for easy circumstances, however it’s not versatile, scalable, or life like.Another choice is to have an exterior logic analyzer with superior options that may show and depict these indicators’ habits, nevertheless it requires exterior and comparatively costly tools.The Built-in Logic Analyzer (ILA) is an alternate that mixes the benefits of each earlier choices. It’s simple, quick, versatile, and has many superior options that assist designers shortly view and verify the chosen indicators’ habits.

Overview

Contents

This text accommodates a number of screenshots from the Vivado GUI. Click on the photographs to make them bigger!Use the sidebar to navigate the define for this tutorial, or scroll down and click on the pop-up navigation button within the top-right nook in case you are utilizing a cell system.

ILA and VIO

The ILA and VIO are free customizable IPs from Xilinx. The ILA IP helps you simply probe inner indicators inside your FPGA and produce them out right into a simulation-like atmosphere to monitor them and confirm their habits.Not like ILA, the VIO IP permits you to just about drive inner indicators inside your FPGA to stimulate or management your design, like driving the RESET sign.

  • Xilinx Mental Property: Built-in Logic Analyzer (ILA)
  • Xilinx Mental Property: Digital Enter/Output (VIO)

Necessities

  • A Xilinx FPGA board
  • The Vivado Design Suite
  • Primary VHDL data

    • I’m utilizing the Kintex-7 FPGA KC705 Analysis Equipment, however the strategies proven on this tutorial ought to work on any fashionable Xilinx FPGA board.

    Obtain the instance mission

    You may obtain the instance mission and VHDL code utilizing the shape beneath. It ought to work in Vivado model 2020.2 or newer.Extract the Zip and open the ila_tutorial.xpr file in Vivado to view the instance design, or learn the remainder of this text to be taught to create it from scratch.

    Create a mission with Vivado

    Begin by opening Vivado. In Vivado’s welcome display screen, click on the Create Challenge button.Click on on Subsequent to proceed.Create a new Vivado projectChange the identify of the mission to ila_tutorial and click on on Subsequent.Be aware: Don’t use areas within the mission identify. As an alternative, use an underscore or sprint.New Vivado project nameSelect RTL mission and uncheck Don’t specify sources right now and click on on Subsequent to proceed.Vivado project typeAdd the supply recordsdata; counter.vhdl and counter_top.vhdl from the design folder. Select VHDL for the goal language. Verify Copy sources into mission and click on on Subsequent to proceed.Vivado add source filesAdd the constraint file prime.xdc from the design folder. Verify Copy constraints recordsdata into mission and click on on Subsequent to proceed.Be aware: this constraint file is restricted to the KC705 board. You want to change the clk pin and the led pin in accordance to your board. And in addition, the -period of your board clock.Vivado add constraint filesSeek for your board and choose it from the checklist. Click on on Subsequent to proceed.Vivado choose your boardThat is the ultimate display screen of the New Challenge wizard. Click on End to open your mission.Vivado new project summary

    The design instance clarification

    We’ll use a easy two-counters chain instance for this tutorial.RTL view of the two cascading countersThe counter.vhdl file accommodates the RTL code for a trivial 4-bit counter that counts from 0 to 15 when enabled. It asserts the 1-bit output when the rely is between 12 and 15. For all different values, the output stays low ‘0’.Right here is the entity interface for the counter module. – – ENTITY DECLARATION. – ENTITY counter IS PORT(clk : IN STD_LOGIC; – Primary clock reset : IN STD_LOGIC; – reset, active_high allow : IN STD_LOGIC; – allow the subsequent counter set off : OUT STD_LOGIC – set off the subsequent counter ); END ENTITY;The counter design has two inner indicators: rely and trigger_o.– rely is used to implement the counting performance.– and trigger_o is an intermediate sign for connecting the output port set off.Don’t fear about ATTRIBUTE, will probably be defined later. – – ARCHITECTURE DECLARATION. – ARCHITECTURE rtl OF counter IS – INTERNAL SIGNALS DECLARATION – SIGNAL rely : UNSIGNED(3 DOWNTO 0) := (OTHERS => ‘0’); SIGNAL trigger_o : STD_LOGIC := ‘0’; – ATTRIBUTE DECLARATION – ATTRIBUTE MARK_DEBUG : STRING; ATTRIBUTE MARK_DEBUG OF rely : SIGNAL IS “true”;Within the itemizing beneath, we see the implementation for the counter. The seq_proc course of is triggered on the rising fringe of the enter port clk and is in reset mode when the enter port reset is excessive ‘1’.The rely sign is incremented when the enter port allow is excessive ‘1’, and the trigger_o sign is asserted excessive when the worth of the sign rely is between 12 and 15. ­ seq_proc: PROCESS (reset, clk) BEGIN – for seq_proc IF (reset = ‘1’) THEN rely <= (OTHERS => ‘0’); trigger_o <= ‘0’; ELSIF rising_edge(clk) THEN IF (allow = ‘1’) THEN rely <= rely + 1; IF (rely > x”B” AND rely <= x”F”) THEN trigger_o <= ‘1’; ELSE trigger_o <= ‘0’; END IF; END IF; END IF; END PROCESS;The file counter_top.vhdl accommodates two instants of the counter linked sequentially.– The counter_1_inst is all the time enabled, and it clocks the counter_2_inst. That’s, the output port set off of counter_1_inst is linked to the enter port clk of counter_2_inst.– The resulted habits is that counter_1_inst prompts counter_2_inst solely 4 out of 16 clock cycles. Thus, counter_2_inst will increment its counter 4 occasions every 16 counts.VHDL code showing two counter instances

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    Creating the VIO core for RESET

    Now that you just perceive the design instance, we’ll create a VIO to management the enter port reset. That may give us the power to manipulate (toggle) the reset from Vivado IDE so we are able to manually management when to begin/cease the counters.Click on on IP Catalog, then seek for VIO, then double-click on VIO (Digital Enter/Output).Vivado IP Catalog: VIO (Virtual Input/Output)First, we modify the identify to vio_reset.Second, we solely want an output port for the reset, so we put 0 within the enter probe rely field, and we put 1 within the output probe rely field.Vivado Customize IP: VIO (Virtual Input/Output)Click on on the PROBE_OUT port tab. As reset is a 1-bit sign, we put 1 within the probe_width field, and we additionally put 0x1 within the preliminary worth field so it begins with excessive ‘1’. Then click on on OK and Generate. Vivado will now start synthesizing the VIO.VIO (Virtual Input/Output) PROBE_OUT portsAfter Vivado finishes synthesizing the VIO, we want to add it to our design by declaring a element for it and instantiating it within the counter_top.vhdl file as beneath.First, add a element declaration for the vio_reset within the element declaration part within the counter_top.vhdl file. – Declare vio_reset COMPONENT vio_reset PORT( clk : IN STD_LOGIC; probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT;Now, the VIO is full, and we’re prepared to synthesize the design. However earlier than that, we want to change the synthesis setting flatten_hierarchy to None.Vivado synthesis settings: flatten_hierarchyClick on on Run Synthesis after which on OK.Vivado: Run SynthesisWhen Vivado finishes synthesis, click on on Open Synthesized Design.Vivado: Open Synthesized DesignChange the format to debug by clicking on Structure after which Debug.

    Inserting debugging probe circulation

    Our synthesized design now accommodates the vio_reset occasion, and it’s time to specify the indicators that we wish to probe. There are 3 ways to try this:

  • Insertion from VHDL file
  • Insertion from the Netlist
  • Insertion from xdc/tcl file

    • We’ll use the primary two strategies and depart the third for a later tutorial.

    Insertion from VHDL file

    This methodology is the simplest and quickest manner to insert a probe, particularly when it’s a composite kind (array or report). Nevertheless it requires including code to the design recordsdata, VHDL code that’s redundant in the actual product.We are able to insert a probe within the VHDL design file by:

  • Declaring a particular attribute known as MARK_DEBUG
  • Connect the sign that we wish to probe with this attribute
  • And activate it by giving it the worth “true” as beneath:

    • – ATTRIBUTE DECLARATION – ATTRIBUTE MARK_DEBUG : STRING; ATTRIBUTE MARK_DEBUG OF rely : SIGNAL IS “true”;Be aware: we solely want to declare the attribute as soon as in every VHDL design file, permitting us to connect it to a number of indicators.Read more: Meeting the Dalai Lama: Everything You Need to KnowWe are able to see from the synthesized design that the sign rely in each counter_1_inst and counter_2_inst are listed underneath Unassigned Debug Nets and marked with a bug icon in each the Netlist and the Schematic.Vivado: Unassigned Debug Nets

    Insertion from the Netlist

    This insertion methodology can be simple, nevertheless it requires that you just first synthesize the design after which manually click on on every sign to mark it for debugging. It might be exhausting if the design is massive and also you need to monitor many indicators.We’ll probe the output port set off in each counters utilizing the Netlist. We are able to do that both from the Netlist window or the Schematic by finding the sign internet after which right-click on it and select Mark Debug.From the Netlist window, discover set off underneath counter_1_inst → Nets → set off. Then, right-click on it and select Mark Debug.Vivado: Mark DebugFrom the Schematic window, discover set off output from counter_2_inst. Then, right-click on it and select Mark Debug.Mark trigger as debug in VivadoWe are able to see that they now are listed underneath Unassigned Debug Nets.Debug tab in Vivado

    Creating the ILA debug core

    Now it’s time to create the ILA debug core. We want to create a probe for every sign that we wish to analyze. The best manner is to reap the benefits of Vivado wizard Set Up Debug.Click on on Set Up Debug after which click on on Subsequent.Vivado: Set Up DebugVivado will checklist all of the debug indicators and seize the clock area for you routinely. Right here we see that our 4 indicators are listed. You may take away the indicators that you’re not occupied with or add additional indicators, however we’ll use all of them.Be aware: we don’t have to use all of the indicators that we’ve marked as Debug.Click on on Subsequent.Vivado: Nets to DebugNow we configure the ILA by selecting the FIFO depth and checking Seize management. We are able to depart the FIFO at 1024 as it’s sufficient depth for our instance.Click on on Subsequent.Vivado: Trigger and Storage Settings / Capture controlNow we see that Vivado discovered one clock and can create one debug core.Click on on End.Vivado: Set Up Debug SummaryWe are able to now see an ILA debug core with 4 probes added to the debug tab and the Netlist window.Vivado Debug tab showing probesIMPORTANT: It is rather essential to save the constraint on this stage so it may be added to the design. In any other case, we danger shedding our ILA core.Click on the Save icon or hit Ctrl+S.Vivado: Out of Date DesignTitle the file ila_core and click on OK.Vivado: Save ConstraintsThe ila_core.xdc file will likely be added to the constraint, and it contains the code and settings for the ILA.Allow us to check out the file content material. You may open the file by going to the Supply window → increase the constraint folder → increase constr_1.First, we see that the file provides a debug attribute to the indicators that we marked debug utilizing the Netlist insertion.Subsequent, we see the creation and configuration of an ILA core.create_debug_core set_propertySubsequent, we see the creation, configuration, and connection for every probe.Create a probe for u_ila_0Subsequent, we see the creation of a debug hub (dbg_hub).set_property C_CLK_INPUT_FREQ_HZThe debug hub is accountable for the communication between Vivado IDE and the debug cores (ILA and VIO). We see that it defines a clock frequency (default is 300 MHz). You want to change that clock to match your clock frequency and save the file.Be aware: the clock linked to ILA and Debug_hub have to be a free-running clock.Now, the ILA is accomplished and saved. We want to rerun the synthesis so the ILA will be added to the synthesized design.Click on Run Synthesis after which on OK.When Vivado finishes working the synthesis, click on on Open Synthesized Design after which on Schematic.We are able to see now that Vivado has added the ILA and Debug_Hub to our design and has linked the debug indicators to the ILA probes.Vivado synthesized design schematicsNow we’re prepared to implement our design and generate the bitstream so we are able to check our design.Click on on Run Implementation after which on OK.Vivado: Launch RunsAfter Vivado end working the implementation, click on on Generate Bitstream after which on OK.Vivado: launch runsAfter Vivado finishes producing the bitstream, click on on Open {Hardware} Supervisor after which on Open Goal, and eventually on Auto join.Open Hardware Manager: Auto ConnectSubsequent, we want to program the FPGA with the bit file (*.bit) and the debug probe file (*.ltx). Vivado routinely finds them for you.Click on on Program System after which on Program.Vivado Hardware Manager: Program Device

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    Configuring the ILA triggers

    After programming the system, we are able to see that Vivado’s GUI format has modified, and a brand new hw_ila_1 dashboard has opened, containing a number of home windows.We’ll reduce some home windows that we don’t want so we are able to work comfortably.Vivado Hardware Manager: ILA viewFrom the dashboard choices, verify hw_vio_1 and uncheck Seize Setup.Additionally, shut the hw_vios tab as a result of once we checked hw_vio_1, it has been added to the Set off setup window.Vivado Hardware Manager: VIO Dashboard OptionsNow, we want to add the reset button to the VIO so we are able to management the reset.Click on on hw_vio_1 after which add reset as proven within the image beneath.Vivado ILA: Add probesWe are able to see that hw_vio_1 now accommodates the reset probe.Read more: how to download drm protected videosChange the worth of the reset in vio_reset to 1 if it’s not 1.Now, we’ll add the triggers that we’ll use. A change of worth on a set off sign will trigger the ILA to begin recording the probed indicators.Allow us to say that we wish to set off (begin recording) on the rising fringe of the output port set off of counter_1_inst. To do this, comply with these steps:

  • Go to the Set off Setup – hw_ila_1 window
  • Click on on the + icon to add a brand new set off and select counter_1_inst/set off and click on on OK.

    • Add the trigger signals as a probe

  • We are able to see that the set off has been added, and now we want to arrange the situation. Click on on the Worth field and select R(0 to 1 transition). Click on on the Operator field and select == (equal)

    • We can even change the set off place to 32, that means that it’ll report 32 samples earlier than the set off occasion as well as to what comes after.Now, the set off is about up and prepared to be armed.Vivado ILA: Capture Mode SettingsNow, we transfer to the waveform window to add the indicators that we wish to view. First, let’s maximize the internal window to acquire a greater view.Second, we want to add some lacking indicators to the probe. Vivado often provides all of the assigned indicators routinely, however on this case, it didn’t.Vivado ILA waveform: Add probesNow, we modify the radix of the rely sign to Unsigned as it’s simpler to comply with.Proper-click on the rely sign identify after which select radix after which Unsigned.Change radix in the Vivado ILA waveform

    Working the ILA and VIO

    Now, we’ve completed configuring and customizing the ILA, and we’re prepared to run it.ILA has two working modes: Speedy and set off.Speedy modeSpeedy mode triggers the ILA instantly and begins recording the samples immediately till the FIFO is full.Click on on the Run set off rapid button.We are able to now see the recorded samples within the waveform window. We see that each rely indicators are 0, and each set off indicators are low ‘0’ as a result of the reset is energetic.Signal transition in the Vivado ILA waveformSet off modeSet off mode requires that we arrange a situation for at the least one set off and arm it. The ILA will preserve ready for the armed set off’s situation to change into true, after which it would begin recording the samples immediately till the FIFO is full.We’ve got already added the set off and set it up to R(0 to 1 transition).

    Working ILA with one set off

    Change reset again to 1 from vio_reset.Vivado ILA: Change the trigger valueClick on on the window Standing hw_ila_1. We see that the core standing is Idle as there are not any triggers armed. Click on on the Run set off button, and that may arm the set off.We see now that the core standing modified to ready for set off. Because the reset is excessive, there is no such thing as a exercise on our set off sign (port set off of counter_1_inst), and ILA is ready.Vivado ILA: Core StatusNow, allow us to change the reset to 0 in order that the counters begin working.Change value of the reset VIO signalWe see now the ILA has acquired triggered and has recorded the samples, and the core standing modified again to Idle.We see the purple vertical line (marker) on the rising fringe of our set off sign (port set off of counter_1_inst), and it’s in place 32. We can also confirm that the sign rely is behaving appropriately and the sign counter_1_inst/set off is excessive for 4 clock cycles between 12 and 15 (the output is delayed by one clock cycle).ILA trigger in the Vivado waveformIf we zoom out a bit bit, we are able to additionally confirm the habits of rely and set off indicators for counter_2_inst.Vivado waveform showing recorded ILA data

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    Working ILA with a number of triggers

    We are able to use a mix of triggers for complicated or superior situations. To seize a number of disjoint time frames in the identical waveform, we are able to use a number of triggers that fireplace repeatedly.For instance, let’s say we wish to set off when the rely sign from counter_1_inst is equal to 9 (rely == 9) and when the rely sign from counter_2_inst is larger than 2 (rely > 2). To do this and cut up the FIFO into 4 time home windows, comply with these steps:

  • Change reset again to 1 from vio_reset
  • Take away the earlier set off probe:

    • Remove selected probe(s) (Delete)

  • Add each rely indicators as triggers:

    • Add Probes

  • Configure the sign rely for counter_1_inst to (rely == 9):

    • Changing value in Trigger Setup

  • Configure the sign rely for counter_2_inst to (rely > 2):

    • Changing the second count trigger valueILA trigger: greater than

  • Configure the variety of home windows to 4 and FIFO depth to 256, and place to 32.

    • ILA trigger settings

  • Click on on the Run set off button, and that may arm the set off. Discover that within the window Standing hw_ila_1, the seize standing is now window 1 of 4 as a result of we’ve 4 home windows.

    • Change reset again to 0 from vio_reset.Vivado ILA core statusMaximize the waveform window. We see now that we’ve 4 home windows and a set off related to every window. Discover that these home windows are unbiased and never steady.The ILA waits for the set off occasion to occur, and when it does, the ILA makes use of the primary window to report 256 samples. It then instantly waits for the subsequent set off till all of the home windows are full.ILA waveform with four time windows and multiple triggers

    Working ILA with Auto re-trigger mode

    ILA has a pleasant function known as Auto re-trigger that may routinely arm the set off after it will get triggered. It’s helpful when monitoring occasions that happen seldom and also you need to run a check in a single day. Or you’ll be able to use it when the set off occurs so typically and quick that you just can not arm the set off manually to seize the samples repeatedly.Allow us to assume that the output port set off of counter_2_inst will get asserted each 3 hours, and also you need to report the info every time it occurs. To use the Auto set off, comply with these steps:

  • Change reset again to 1 from vio_reset
  • Take away the earlier set off probe
  • Add trigger_2_OBUF sign as set off:

    • Vivado: Add trigger_2 probe

  • Configure the set off to the situation to equal (==) and falling edge F(1-to-0 transition)
  • Configure the variety of home windows to 1 and FIFO depth to 1024, and place to 32:

    • ILA trigger: F (1-to-0 transition)

  • Click on on Auto re-trigger button:

    • Toggle auto re-trigger mode for this ILA core

  • Lastly, change reset again to 0 from vio_reset:

    • Change reset trigger level in ILAWe are able to see now that the waveform window is getting refreshed and up to date because the set off occur. It’s quick, however the habits is noticeable.Click on on Cease set off and toggle Auto re-trigger.

    Working ILA with Seize mode

    One other function of ILA is the Seize mode. In some circumstances, you aren’t occupied with recording all the info however fairly seize a particular pattern. Seize mode helps you filter out information and report solely the samples you have an interest in.Let’s say we’re solely occupied with sampling when the output port set off of counter_1_inst is ‘1’ AND the output port set off of counter_2_inst is ‘0’.To use Seize mode to obtain this, comply with these steps:

  • Change reset again to 1 from vio_reset
  • Take away the earlier set off probe
  • From the dashboard, Uncheck Set off Setup and verify Seize Setup. Discover {that a} Seize Setup window will seem. From the Settings – hw_ila_1 window, Change Seize mode to BASIC, the window to 1, the FIFO depth to 1024, and place to 1:

    • Vivado ILA: Capture Mode Settings

  • Add trigger_2_OBUF, and counter_1_inst/set off from the Seize Setup window:

    • Add trigger and trigger_2 signals to ILA

  • Configure counter_1_inst/set off to the situation equal (==) and 1 (logical one):

    • Change trigger level to "1 (logical one)"

  • Configure trigger_2_OBUF to the situation equal (==) and 0 (logical zero):

    • Change trigger_2 level to "0 (logical zero)"

  • Change the Seize Situation to International AND:

    • Set Capture Condition to Global AND

  • Click on on the Run set off button after which change reset to 0 from vio_reset:

    • Set reset ILA trigger value to "[B] 0"As we are able to see from the picture beneath, the waveform has solely recorded information when counter_1_inst’s rely sign is 13, 14, 15, or 0. Every other counts are filtered out as a result of counter_1_inst/set off is excessive on these counts solely.Filtered ILA samples using Capture mode in vivado

    Conclusion

    On this tutorial, we realized about ILA and VIO and totally different use-cases for them. ILA and VIO are wonderful choices for on-chip debugging. They’re free, simple to use, versatile, scalable, and easy but supply superior options. The use of a number of triggers and Seize mode helps you obtain a posh debugging scheme.Read more: Overwatch How to get out of bronze league | Top Q&A

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